End of lithography at 32 nm?, *

[treck]

The word line acts as middle terminal for a vertical transistor, but becomes too resistive if

[guiding_light]

www.btbmarketing.com/iedm/releases/IEDM_2011_tip_sheet.doc

15-nm NAND Technology Unveiled: Last year’s IEDM saw the unveiling of the world’s first NAND memory built using 25-nm design rules. This year, Hynix Semiconductor researchers have demonstrated mid-1x nm NAND flash memories with excellent electrical characteristics and reliability. To overcome scaling challenges of mid-1x nm NAND devices, new integration technologies have been developed such as a quad-spacer-patterning approach (QSPT), advanced WL air-gap and floating gate slimming processes. A new N±1WL Vpass scheme can mitigate the WL-to-WL high field due to scaling, and improve programming speed and charge loss. (Paper #9.1, “A Middle-1X-nm NAND Flash Memory Cell (M1X-NAND) with Highly Manufacturable Integration Technologies,” J. Hwang et al, Hynix Semiconductor)