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Posted: Jun 21 2004, 09:32 PM
I have a very general question (aren't they always the most difficult to
I have some education in semiconductor technology (solid state physics,
microelectronic circuit design), so I am not a total newbie.
What I am after is a snapshot of today's technology: both what is on the
marketplace, and what is in the immediate future to enter the marketplace
(i.e., not nanotube transistors). Here is my set of questions. Any help
would be much appreciated.
1. What is the chemical composition of most ICs today? In other words,
what materials are most used, (besides Si).
Breaking it down, we have,
the PN Junction, :
the Substrate, :
the Wire Interconnects, :
and the Dielectrics.:
2. Now that we have the materials, what sizes are most popular,
and what structures are relevant to performance concerning their
sizes? (transistor gate length, width; interconnect wire width, spacing;
3. Is CMOS "THE" defacto technology for microelectronic circuits today?
Is BPJ even relevant anymore?
4. Once a circuit topology is completed, and the technology is agreed
upon, what is the item that goes to the foundry?
Is it a set of files using the foundry's proprietary software, or an
agreed upon standard file format which one can make from a variety of
Thanks for your input. I know this is a wierd totally academic question
asking things that probably no one person can answer.
If you can point me to any resources that would help me, that would be most
appreciated as well.
I am not using you for a school or work-related study, I am just an
unemployed computer engineer with a Bachelor's degree, withering away in the
midwest losing all touch with what is going on in industry. But I am
studying my butt off trying to keep sharp. This is part of that endeavour.
Thanks for your time.
Posted: Jun 21 2004, 09:35 PM
AFAIK, boron is the most commonly used P-type dopant, and just about the
only practical p-type dopant for silicon. (Boron is often introduced as
a BF2 ion rather than as atomic or ionic boron. Older technologies
often used boron nitride (nitrate?) solid sources.) AFAIK, phosphorus
and arsenic are the most commonly used n-type dopants in silicon.
Common sources for phosphorous are POCl3 vapor and PH3 (phosphine) gas.
Probably the most common source for arsenic is AsH3 (arsine) gas.
Recognize that doping levels are such that it takes extremely precise
(and expensive) technology to tell the difference between atomically
pure silicon and silicon which has been doped n-type or p-type to
Silicon, usually doped weakly n-type or p-type, depending on the
Aluminum, generally with around 0.5% to 5% copper. Straight copper is
the wave of the future, though.
Silicon dioxide, although some "high-k" (high dielectric constant)
materials such as hafnium oxide are coming in to play for gate oxides,
as well as "low-k" materials (the most exotic I've heard of is aerojels)
for upper level (interconnect) dielectrics.
How much money do you want to spend and how much performance do you
need? Also, are you doing digital or analog?
Gate lengths range from 90nm (leading-edge production) to, oh, 3 or 4um.
(Before anyone scoffs at a fab still making 3um or 4um gates, I was,
briefly, part of a team investigating the possibility of bringing a
process like that back to life. The end customer found it was cheaper
to bring the process back to life than to redesign, and more
importantly, requalify, their part in a newer technology.)
Gate widths depend on how much current you need to drive your loads.
Could be anywhere from 0.5um (or less) to a few hundred um.
Interconnect wire widths will depend on the level and the general
process technology. Probably around 1um, maybe less, for first and
second level interconnects in a new technology, to around 5 to 10um for
top level interconnects in an older technology.
I'm not quite sure what you mean by "spacing". I'm going to assume the
spacing between interonnect lines. That's generally around 0.5x to 1x
the interconnect linewidth.
CMOS is certainly the dominant technology. BJT still fill a niche,
though, especially (IMHO) for analog and when you need the absolutely
I *think* generally a standard file format called GDSII. There are only
a few vendors of layout tools (Cadence, Mentor Graphics, maybe some
others), so this isn't too hard (again, IMHO) to do / to make happen.
The April 2004 issue of Scientific American had a good review article on
the state of the art in IC technology. You might want to take a look
at it. As far as textbooks / reference books, probably your best bet is
to see what the local engineering school is using for an undergrad text.
Failing that, see what your alma mater is using. Recognize that a
class on semiconductor device physics will almost certainly use a
different book than a class IC processing.
You're welcome. Hope this helps.
Posted: Jun 21 2004, 09:36 PM
After posting this, I realized this wasn't quite what I meant to say.
Probably a better way of putting it is that if you want an accurate
quantitative measurement of typical doping levels, it will require
fairly precise and expensive technology.
If you're willing to settle for "factor of 2" or "order of magnitude"
type measurements, that can be done reasonably cheaply.
Posted: Jul 16 2004, 09:22 PM
Wow! Great summary!
A couple comments:
Mr. Pownall's post described most current commodity IC methods.
Advanced methods such as strained silicon, SOI, ALD substrates,
carbon-based interconnects, optical interconnects, Si-O-N
dielectrics, etc., are being used in advanced ICs and will become
more common in commodity ICs over time.
Posted: Jul 16 2004, 09:23 PM
Glad to hear that you found it useful / interesting. It's nice to get
feedback, especially positive feedback. (So often, I post something in
response to a question here, or in some other group, and never hear
anything - Did my answer solve the original poster's problem? Did the
OP find a better solution? If so, what? etc.)
I should have mentioned strained silicon. As you say, that's playing a
bigger and bigger role. I'm not as positive / optimistic as you about
C-based interconnects or optical interconnects; I think the cost/benefit
ratio, and especially the problem/benefit ratio, is going to stay too
high. But hey, I've been wrong before, and I'm could be wrong here as
well. Being right about a trend when everybody else thinks otherwise is
how you make the big bucks. (Caveat: I'm speaking about on-chip optical
interconnects. Chip to chip, and especially board-to-board optical
interconnects, are an almost sure thing, IMHO, given the the current
state of the art.)
I don't believe I've ever even heard the term "ALD substrate" - can you
Posted: Jul 16 2004, 09:23 PM
Sorry about that. I used my original "Thank You" in lieu.
Your answer was great, and detailed, and it did answer my questions. Thanks
for spending the time and effort.
I assume that circuit designers have the process parameters embedded in the
simulation tools they are using for their design.
There is so much information to keep track of, since I am currently
"out-of-the-loop" I don't know how the management structure handles the
information flow from fab to design. In other words, a 13um process would
have different characteristics than a 90nm process, and the designers would
not have to know all of the characteristics in order to design their
circuits? - the simulaton tools would implicitly know that.? So management
would have to make sure that the designers had the most relevant simulation
tools at their disposal....
I am just curious how information flows from device physics to process
engineers to management to circuit designers. I guess I will find out soon
Posted: Jul 16 2004, 09:24 PM
IC design isn't really my area; I was more on the manufacturing side of
That said, I *think* the layout software packages usually have something
called a "technology file" that contains information about physical
parameters such as min/max line widths, min/max line spaces, number of
interconnect levels, etc, as well as electrical parameters such as
intra-layer capacitance per unit area / unit length, inter-layer
capacitance per unt area / unit length, threshold voltages, sheet
resistivities, drive current per unit width, etc.
The decision about what process technology to use is made well before
the layout starts. Generally, the most recent technology is used, but
the design might be done in an older technology for cost (doing a design
in a process, and fab, that's already fully depreciated and paid for can
be a big cost savings), fab capacity (if the part is expected to be a
high volume runner, you may not want to put it in a fab that's already
full), compatibility with other parts (not much point, IMHO, in
designing a part in a 2.5V process when everything else on the circuit
board is a 3.3V process, unless you can get the 2.5V supply for free, or
at least cheap.) or other reasons.
Information flow, in my experience, is generally from the people doing
the process development to the people doing the technology file
development (often, those are the same people) and later, after the
process is released to production, to the process engineers supporing
the process. Again, in my experience, there's not a whole lot of
interaction between the IC designers and the process engineers unless
there's some kind of problem: "Your circuit always fails the ICT2S test
at functional if the threshold voltage is in the lower third of the spec
band", "I know the process is spec'd for 0.2pF/V, but it's more like
0.25pF/V". The interaction between the chip designers and the process
designers is usually, in my experience, things like "We could really use
X in the next process generation", while the interaction between the
process engineers and the process designers are usually things like
"This is really hard to do with the existing toolset" and "We're not
going to be able to do that unless we get this new piece of equipment /
the equipment vendor has a breakthrough".
Hope this helps.
Posted: Jul 21 2004, 07:13 PM
(Atomic Layer Deposition) It's just a fancy name for epitaxy.
Exotic interconnects are still in the research phase but there is
LOTS of interest (and funding). I know groups that are working on
three distinct different kinds.
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